Modern electronic devices such as a notebook computer comprise a variety of memories to store information. Memory circuits include two major categories. One is volatile memories; the other is non-volatile memories. Volatile memories include random access memory (RAM), which can be further divided into two sub-categories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they will lose the information they store when they are not powered. On the other hand, non-volatile memories can keep data stored on them permanently unless an electrical charge is applied to non-volatile memories. Non-volatile memories include a variety of sub-categories, such as electrically erasable programmable read-only memory (EEPROM) and flash memory.
SRAM cells may comprise different numbers of transistors. According to the total number of transistors in an SRAM cell, the SRAM cell may be referred to as a six-transistor (6-T) SRAM, an eight-transistor (8-T) SRAM, and the like. SRAM cells are arranged in rows and columns. An SRAM cell is selected during either a READ operation or a WRITE operation by selecting its row and column. In a READ operation, both BL and BL of an SRAM cell are pre-charged to a voltage approximately equal to the operating voltage of the memory bank in which the SRAM cell is located. In response to a binary code from the row decoder, a word line coupled to the SRAM cell to be read is asserted so that the data latch is selected to proceed to a READ operation. During a READ operation, through a turned on pass-gate transistor, one bit line coupled to the storage node storing a logic “0” is discharged to a lower voltage. Meanwhile, the other bit line remains at the pre-charged voltage because there is no discharging path between the other bit line and the storage node storing a logic “1”. The differential voltage between BL and BL (approximately in a range from 50 to 100 mV) is detected by a sense amplifier. Furthermore, the sense amplifier amplifies the differential voltage to a logic state level and reports the logic state of the memory cell via a data buffer.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.